Asim Majeed Murshid Khalil

Full Name: Asim Majeed Murshid Khalil

Email Address: This email address is being protected from spambots. You need JavaScript enabled to view it.

Certificate: Doctorate

Scientific title: Professor

General Specialization: Electronic engineering

Accurate Specialization: Precise electronics

 Scientific Links:

1- https://scholar.google.com/citations?hl=ar&user=mkiRTvgAAAAJ

2- https://www.researchgate.net/profile/Asim-Murshid

 published Research:

1. List of Publications:
1.1 Steganography: Hiding Text Within Image, Kirkuk University Journal Scientific Studies, Vol. 3, No. 2, pp. 70-87, 2008.
1.2 VLSI Architecture of Fuzzy Logic Hardware Implementation: a Review, Springer - International Journal of Fuzzy Systems, Vol. 13, No. 2, pp. 74-88, June 2011.
1.3 A Novel VLSI Architecture for a Fuzzy Inference Processor using Triangular-Shaped Membership Function, Springer - International Journal of Fuzzy Systems, Vol. 14, No. 3, pp. 345-360, Sep. 2012.
1.4 A Novel VLSI Architecture for a Fuzzy Inference Processor using Gaussian-Shaped Membership Function, Journal of Intelligent and Fuzzy Systems, Vol. 24, No. 1, pp. 5-19, 2013.
1.5 A Novel Multi Membership Function Based VLSI Architecture of a Fuzzy Inference Processor, Springer - International journal of Fuzzy Systems, Vol. 16, No. 4, pp. 468-482, Dec. 2014.
1.6 FPGA Implementation of Mean – Max Membership based Defuzzifier Unit, Kirkuk University Journal/Scientific Studies (KUJSS), Vol.10, Isuue 3, pp. 79-91, Sep. 2015.
1.7 Center of Sums based Defuzzifier Unit VLSI Architecture, Tikrit Journal of Pure Science,Vol.21, No. 1, pp.87-94, Jan. 2016
1.8 Direct Torque Control of Induction Motor with Matrix Converter, Journal of Engineering Science and Technology Review, Vol.9, No.2, pp.50-58, 2016.
1.9 Center of Largest Area Defuzzifier Unit VLSI Architecture, Tikrit Journal of Pure Science, Vol.21, No. 6, pp.160-166, Sep. 2016.
1.10 Device and Circuit level performance assessment of n and p type dopingless MOSFETs, International Journal of Numerical Modelling-Electronic Networks devices and fields, Vol.32, No. 2, pp.1-11, March. 2019.
1.11 Impact of Pocket doping on the performance of Planar SOI Junctionless Transistor, Silicon, Vol.13, No. 6, pp.1771-1776, June, 2021.
1.12 Metal Controlled Nanoscaled Dopingless MOSFET on Selective/Partial Buried Oxide, IET Circuits, Devices & Systems, Vol.14, No.7, pp.1058-1064, Oct., 2020.
1.13 Ground plane and selective buried oxide based planar junctionless transistor, Frequenz, Vol.76, No.(1-2), pp.1-7, 2022.