أ.د. عاصم مجيد مرشد خليل

الأسم الثلاثي: عاصم مجيد مرشد

البريد الالكتروني: عنوان البريد الإلكتروني هذا محمي من روبوتات السبام. يجب عليك تفعيل الجافاسكربت لرؤيته.

الشهادة: دكتوراه 

اللقب العلمي: أستاذ

الاختصاص العام: هندسة الكترونيك

الاختصاص الدقيق: الكترونيك دقيق

الجهة المانحة للشهادة (الجامعة، الكلية، القسم): الهند / الجامعة الملية الاسلامية / كلية الهندسة والتكنولوجيا

تاريخ الحصول على الشهادة: 2013

الروابط العلمية: 

1- https://scholar.google.com/citations?hl=ar&user=mkiRTvgAAAAJ

2- https://www.researchgate.net/profile/Asim-Murshid

 المؤتمرات التي تم المشاركة فيها:

Publications in International Conference:
1.14 Architectural Design of Fuzzy Inference Processor using Triangular-Shaped Membership function, in proceeding of IEEE International Conference On Open System, Malaysia, Langkawi, 25-28, September, 2011.
1.15 A Novel Fuzzy Inference Processor using Trapezoidal-Shaped Membership function, in proceeding of IEEE International Conference On Open System, Malaysia, Langkawi, 25-28, September, 2011.
1.16 A Novel VLSI Architecture of a Defuzzifier Unit for a fuzzy Inference processor, in proceeding of IEEE International Conference Of Advanced Electronic Systems, India, Pilani, 21-23, September, 2013.
1.17 A Novel VLSI Architecture of a Multi Membership function based Max-Min calculator circuit, in proceeding of IEEE International Conference Of Advanced Electronic Systems, India, Pilani, 21-23, September, 2013.
1.18 A Novel VLSI Architecture of a Weighted Average Method based Defuzzifier Unit, in proceeding of IAENG International Multi Conference of Engineers and Computer Scientists, Hong Kong, 12-14, March, 2014.
1.19 Design of a Novel High Gain Carbon Nanotube based operational Transconductance Amplifier, in proceeding of IAENG International Multi Conference of Engineers and Computer Scientists, Hong Kong, 12-14, March, 2014.
1.20 A Novel High Performance Nanoscaled Dopingless Lateral PNP Transistor on Silicon on Insulator, in proceeding of IAENG International Multi Conference of Engineers and Computer Scientists, Hong Kong, 12-14, March, 2014.
1.21 High Performance Oxide Engineered Lateral Schottky Bipolar Transistor, in proceeding of IAENG International Multi Conference of Engineers and Computer Scientists, Hong Kong, 12-14, March, 2014.
1.22 High performance carbon Nanotube based Cascade operational Transconductance Amplifier, in proceeding of the World Congress on Engineering 2014 Vol. I, WCE 2014, July 2 - 4, 2014, London, U.K.
1.23 A novel High Performance Nanoscaled Dual Oxide Doping less Tunnel field Effect Transistor, in Proceeding of the World Congress on Engineering 2014 Vol. I, WCE 2014, July 2 - 4, 2014, London, U.K.
1.24 Schottky barrier based compact transmission gate: a simulation study, in Proceeding of IEEE 3rd International Conference on Devices, Circuits & Systems, India, Coimbatore 3-5 March 2016.
1.25 A novel hybrid doping based SOI MOSFET, in Proceeding of IEEE 3rd International Conference on Devices, Circuits & Systems, India, Coimbatore 3-5 March 2016.
1.26 Charge plasma based Partial-Ground-Plane-MOSFET on Selective Buried Oxide (SELBOX), in Proceeding of IEEE International Conference on Silicon On Insulator, U.S.A., San Francisco, 10-13 Oct. 2016.
1.27 Polarization Engineered Enhancement Mode High Breakdown Voltage GaN CAVET, in proceeding of the 9th IEEE GCC Conference & Exhibition, Bahrain, Manama, 8-11 May, 2017.
1.28 High performance Carbon Nanotube based folded Cascode Operational Transconductance Amplifiers, in Proceeding of IEEE International Conference on Multimedia, Signal processing and Communication Technology (IMPACT 2017), India, Aligarh 24-26 Nov. 2017.
1.29 Hybrid Doped PMOS and its Short Channel Performance, in Proceeding of 14th IEEE India Council International Conference (INDICON), India, Roorkee, (15-17) Dec. 2017.
1.30 Silicon on insulator Junction less transistor with high work function metal under buried oxide layer, 5th International Conference on Nanotechnology for Better Living (NBL-2019), India, Srinagar, (7-11) Apr. 2019.

1.31 Design and Simulation of High Performance Dopingless Tunnel Diode, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), U.S.A., San Jose, CA, (14-17) Oct. 2019

1.32 Si / SiGe Material based doping free Tunnel FET, International Virtual Conference on Reimagining Artificial Intelligence (AI) for Smart Community, Malaysia and India, 17-18 December 2020.

الدورات  التي تم المشاركة فيها:

2.1 Training program for the Establishment of Infrastructure of 18 Universities in Iraq organized by the KTNET and the Korea International Cooperation Agency (KOICA) of the Republic of Korea from ( 9 – 22) November 2007

البحوث المنشورة:

1. List of Publications:
1.1 Steganography: Hiding Text Within Image, Kirkuk University Journal Scientific Studies, Vol. 3, No. 2, pp. 70-87, 2008.
1.2 VLSI Architecture of Fuzzy Logic Hardware Implementation: a Review, Springer - International Journal of Fuzzy Systems, Vol. 13, No. 2, pp. 74-88, June 2011.
1.3 A Novel VLSI Architecture for a Fuzzy Inference Processor using Triangular-Shaped Membership Function, Springer - International Journal of Fuzzy Systems, Vol. 14, No. 3, pp. 345-360, Sep. 2012.
1.4 A Novel VLSI Architecture for a Fuzzy Inference Processor using Gaussian-Shaped Membership Function, Journal of Intelligent and Fuzzy Systems, Vol. 24, No. 1, pp. 5-19, 2013.
1.5 A Novel Multi Membership Function Based VLSI Architecture of a Fuzzy Inference Processor, Springer - International journal of Fuzzy Systems, Vol. 16, No. 4, pp. 468-482, Dec. 2014.
1.6 FPGA Implementation of Mean – Max Membership based Defuzzifier Unit, Kirkuk University Journal/Scientific Studies (KUJSS), Vol.10, Isuue 3, pp. 79-91, Sep. 2015.
1.7 Center of Sums based Defuzzifier Unit VLSI Architecture, Tikrit Journal of Pure Science,Vol.21, No. 1, pp.87-94, Jan. 2016
1.8 Direct Torque Control of Induction Motor with Matrix Converter, Journal of Engineering Science and Technology Review, Vol.9, No.2, pp.50-58, 2016.
1.9 Center of Largest Area Defuzzifier Unit VLSI Architecture, Tikrit Journal of Pure Science, Vol.21, No. 6, pp.160-166, Sep. 2016.
1.10 Device and Circuit level performance assessment of n and p type dopingless MOSFETs, International Journal of Numerical Modelling-Electronic Networks devices and fields, Vol.32, No. 2, pp.1-11, March. 2019.
1.11 Impact of Pocket doping on the performance of Planar SOI Junctionless Transistor, Silicon, Vol.13, No. 6, pp.1771-1776, June, 2021.
1.12 Metal Controlled Nanoscaled Dopingless MOSFET on Selective/Partial Buried Oxide, IET Circuits, Devices & Systems, Vol.14, No.7, pp.1058-1064, Oct., 2020.
1.13 Ground plane and selective buried oxide based planar junctionless transistor, Frequenz, Vol.76, No.(1-2), pp.1-7, 2022.